Design and Performance Analysis of Unsigned Multiplier using Faster CSLA

Authors:G. ANANTHAVENKATA REDDY, B. SUJATHA

0355-0358

Clock Gating and Run Time Power Gating Integration by using Variable Body Biasing Technique

Authors:M. APARNA, B. SURESH BABU

0359-0363

PID Controller Implementation for Speed Control Applications using FPGA

Authors:G. SRAVANTHI, N. RAJ KUMAR

0364-0370

Low Power Full adder Design using double Pass-Transistor Asynchronous Adiabatic Logic

Authors:E.ANUSHA, J. PRASAD BABU, SK.MASTHAN BASHA

0371-0374

A Novel Architecture for low Cost and High Speed Finite Impulse Response(FIR) Filter using Distributed Arithmetic

Authors:KOMMIREDDY SUPRAJA, SYED KAREEMSAHEB, SK.MASTHAN BASHA

0375-0378

Optimized Reversible Logic Gate with Energy Efficient Code Converters

Authors:KOTHAPALLY NIKHILA , VENKATA CHARY, N. BHOJANNA, G. SUJATHA

0379-0383

A 4-Bit Full Adder using 10 Transistors with Reduced Leakage Power and Ground Bounce

Authors:TANURKAR POOJA, S. VENKATA CHARY, N. BHOJANNA, G. SUJATHA

0384-0389

FPGA Implementation of Multiband Clock Distributation using VLSI Technology

Authors:B. REDDY THANUJA, RAMESH MALYALA

0390-0394

Privacy Protection Against Wormhole Attack In MANET

Authors:U. ANUSHA RANI, K. C. K. NAIK

0395-0399

Design of Low Swing SRAM Memory Bit Cell for High Speed Applications

Authors:K.GOUTHAMI, R. JAWAHARLAL

0400-0403